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USER’S GUIDE
050396 104/173
105
SECTION 13: PROGRAMMABLE TIMERS
FUNCTIONAL DESCRIPTION
The Secure Microcontroller incorporates two 16–bit tim-
ers called Timer 0 and Timer 1. Both can be used to gen-
erate precise time intervals, measure external pulse
widths, or count externally applied pulses.
Each programmable timer operates either as a “timer”
in which time periodic interrupts may be generated or as
a “counter”, in which the timer register is incremented
when transitions are detected on an external input pin.
When a programmable timer is operating as a “timer”,
the least–significant timer register is incremented once
every machine cycle or at 1/12 the frequency of the
clock oscillator. When a 12 MHz crystal is used, the reg-
ister will be incremented once every 1 µs.
When “counter” operation is selected, the least–signifi-
cant timer register is incremented each time that a
1–to–0 transition is detected on the corresponding input
pin that may be assigned for the timer (T0 for Timer 0, T1
for Timer 1). These pins are the optional function of P3.4
and P3.5 respectively. The timing of the “counter” mode
is internally synchronized to the machine cycles. During
S5P2 of every machine cycle, the external input pin is
sampled. A 1–to–0 transition is defined as a 1 detected
during a machine cycle followed by a 0 detected in the
S5P2 clock phase of the next machine cycle. The new
count value in the timer register will be present during
clock phase S3P1 of the next successive (or third) ma-
chine cycle. See the section on timing for details.
The TMOD and TCON Special Function registers are
used to control the initialization of the two program-
mable timers. A summary of the bits contained in TMOD
is shown in Figure 13–1. The relevant TCON register
bits are depicted in Figure 13–2. Each Timer has four
control bits associated with it including C/T
, GATE, M1,
and M0. C/T=1 selects counter operation and C/T=0 se-
lects timer operation.
A separate GATE bit in the TMOD register is provided
for each timer. These bits enable an associated external
interrupt input pin as a gating control for the timer or
counter function. The P3.2 (INT0
) pin operates in con-
junction with Timer 0 while the P3.3 (INT1) pin operates
with Timer 1. When the Timer Run bit (TRn) and GATE
are both set to a 1, the timer or counter function will be
enabled only during the times that the associated inter-
rupt input pin is at a 1 level. When the Timer function is
selected, the GATE bit provides a means of measuring
the widths of logic 1 pulses applied to the interrupt pin in
units of machine cycles. When the counter function is
selected, the pulse is measured in units of 1–to–0 transi-
tions detected on the external counter input pin.
Both of the programmable timers have M1,M0 control
bits in the TMOD register which are used to select one of
the four operating modes described below.
TMOD REGISTER CONTROL BIT SUMMARY Figure 13–1
Bit Description
TMOD.7 (Timer 1);
TMOD.3 (Timer 0): GATE
“Gate Control”: When set to 1 with TRns=1, timer/counter’s input count pulses will only be
delivered while a 1 is present on the INT
pin. When cleared to 0, counter
pulses will always be received by the timer/counter as long as TRn=1.
Initialization: Cleared to 0 on any reset.
TMOD.6 (Timer 1);
TMOD.2 (Timer 0): C/T
“Counter/Timer Select”: When set to a 1, the counter function is selected for the associated program-
mable timer; when cleared to 0, the timer function is selected.
Initialization: Cleared to 0 on any reset.
- TABLE OF CONTENTS 1
- SECTION 1: INTRODUCTION 2
- SOFTWARE SECURITY 2
- SEPARATE ADDRESS/DATA BUS 2
- LARGE NONVOLATILE MEMORY 3
- IN–SYSTEM LOADING 3
- HIGH RELIABILITY OPERATION 3
- PRODUCT DESCRIPTION 4
- 050396 4/173 5
- SECTION 2: SELECTION GUIDE 6
- 050396 6/173 7
- INTERNAL DATA BUS 8
- INTERNAL ADDRESS BUS 8
- 050396 8/173 9
- Watchdog Timer 10
- Resident Loader ROM 10
- Secure Microcontroller Memory 11
- Organization 11
- Internal Registers 11
- Programmer’s note 12
- Program and Data Memory 13
- 050396 13/173 14
- DS5000 Memory Map Control 16
- 050396 16/173 17
- 050396 17/173 18
- DS5001/DS5002 Memory Mapped 20
- Peripherals 20
- 050396 23/173 24
- 050396 25/173 26
- Special Function Registers 28
- PA3 PA2 PA1 PA0 RA32/8 ECE2 29
- POWER CONTROL REGISTER 31
- 050396 31/173 32
- TIMER CONTROL REGISTER 33
- TIMER MODE REGISTER 34
- SERIAL CONTROL REGISTER 35
- INTERRUPT ENABLE REGISTER 36
- INTERRUPT PRIORITY REGISTER 37
- DS5001 CRC REGISTER 38
- DS5001 MCON REGISTER 40
- 050396 40/173 41
- PROGRAM STATUS WORD REGISTER 42
- 050396 44/173 45
- INSTRUCTION SET 46
- Introduction 46
- Addressing Modes 46
- 050396 46/173 47
- Program Status Flags 48
- 050396 48/173 49
- DATA RETENTION 56
- BATTERY BACKED CIRCUITS 56
- BATTERY ATTACH PROCEDURE 57
- BATTERY LIFETIME 57
- 050396 57/173 58
- LITHIUM BATTERY USAGE 59
- FRESHNESS SEAL 59
- SECTION 7: POWER MANAGEMENT 60
- Idle Mode 60
- Stop Mode 61
- Voltage Monitoring Circuitry 62
- Power Fail Interrupt 63
- Total Power Failure 63
- Partial Power Failures 63
- SECTION 8: SOFTWARE CONTROL 65
- Timed Access 65
- TIMED ACCESS Figure 8–1 65
- 050396 65/173 66
- WATCHDOG TIMER Figure 8–2 68
- WATCHDOG TIMER CONTROL BITS 69
- CRC MEMORY VERIFICATION 69
- 050396 69/173 70
- CRC CODE EXAMPLE Figure 8–3 71
- SECTION 9: FIRMWARE SECURITY 72
- SECURITY OVERVIEW 72
- SECURITY LOCK 73
- RAM Memory 73
- Encrypted Memory 73
- 050396 74/173 75
- Encryption Algorithm 76
- Encryption Key 76
- Dummy Bus Access 77
- On–chip Vector RAM 78
- Self–Destruct Input 78
- Microprobe/Die Top Coating 78
- Random Number Generator 78
- Security Summary by Part 79
- 050396 79/173 80
- Change Code 81
- External Circuits 81
- Tamper Protection 81
- SECTION 10: RESET CONDITIONS 82
- Reset Sources 82
- 050396 82/173 83
- Power On Reset 84
- Power On Reset 85
- External Reset 85
- Watchdog Timer Reset 85
- Memory Map 86
- Interrupts 87
- Protection 88
- SECTION 11: INTERRUPTS 89
- INTERRUPT SOURCES 89
- External Interrupts 90
- Timer Interrupts 90
- Serial Port Interrupts 90
- Power–fail Warning Interrupt 90
- Simulated Interrupts 91
- INTERRUPT PRIORITIES 93
- INTERRUPT ACKNOWLEDGE 94
- 050396 94/173 95
- SECTION 12: PARALLEL I/O 96
- OVERVIEW 96
- PORT 1 FUNCTIONAL CIRCUITRY 97
- PORT 2 FUNCTIONAL CIRCUITRY 97
- PORT 3 FUNCTIONAL CIRCUITRY 98
- OUTPUT FUNCTIONS 98
- INPUT FUNCTION 99
- REPROGRAMMABLE PERIPHERAL 100
- CONTROLLER (RPC) 100
- RPC INTERRUPTS 101
- Bit Description: 102
- RPC PROTOCOL 103
- DMA OPERATION 103
- FUNCTIONAL DESCRIPTION 105
- Bit Description 105
- USER’S GUIDE 106
- 050396 105/173 106
- SECTION 14: SERIAL I/O 110
- FUNCTION DESCRIPTION 110
- SCON.2: RB8 112
- SCON.1: TI 112
- SCON.0: RI 112
- BAUD RATE GENERATION 112
- 050396 112/173 113
- 050396 113/173 114
- TRANSMIT TIMING: 115
- RECEIVE TIMING: 115
- ASYNCHRONOUS OPERATION 116
- Mode 2 and 3 117
- APPLICATION: SERIAL PORT 120
- INITIALIZATION 120
- SERIAL I/O OPERATING MODES 120
- 050396 120/173 121
- 050396 121/173 122
- 050396 122/173 123
- SECTION 15: CPU TIMING 124
- OSCILLATOR 124
- INSTRUCTION TIMING 125
- EXPANDED DATA MEMORY TIMING 129
- SECTION 16: PROGRAM LOADING 130
- INTRODUCTION 130
- INVOKING THE BOOTSTRAP LOADER 130
- DS5000 Series 131
- DS5001/DS5002 Series 131
- EXITING THE LOADER 131
- SERIAL PROGRAM LOAD MODE 133
- AUTO–BAUD RATE DETECTION 134
- COMMAND LINE INTERFACE 135
- COMMAND LINE SYNTAX 135
- COMMAND SUMMARIES 136
- 050396 136/173 137
- Xon/Xoff 138
- DS5002FP COMMANDS 138
- 050396 138/173 139
- INTEL HEX FILE FORMAT 140
- PARALLEL PROGRAM LOAD MODE 142
- PARALLEL PROGRAMMING CONCERNS 143
- RPC PROGRAM MODE OPERATION 143
- SECTION 17: REAL–TIME CLOCK 144
- DS1215 PHANTOM TIME CHIP 144
- 050396 144/173 145
- 050396 146/173 147
- REGISTERS 148
- SPECIAL BITS 148
- 050396 149/173 150
- MEMORY MAP 151
- TIME–OF–DAY ALARM 152
- 050396 152/173 153
- DS1283 RTC INTERRUPTS 154
- (DS1215 EXAMPLE) 155
- 050396 155/173 156
- 050396 156/173 157
- 050396 157/173 158
- (DS1283 EXAMPLE) 159
- 050396 159/173 160
- 050396 160/173 161
- 050396 161/173 162
- 050396 162/173 163
- SECTION 18: TROUBLESHOOTING 164
- UNEXPLAINED DEVICE RESETS 164
- WRONG TIME 164
- 050396 164/173 165
- 050396 165/173 166
- 050396 166/173 167
- 050396 167/173 168
- 050396 168/173 169
- 050396 169/173 170
- 050396 170/173 171
- 050396 171/173 172
- 050396 172/173 173
- OGRAM BRANCHING 174
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Alpine CDE-125BT manuels
Manuels d'utilisation et guides de l'utilisateur pour Systèmes vidéo pour voitures Alpine CDE-125BT.
Nous fournissons des manuels en pdf 7 Alpine CDE-125BT à télécharger gratuitement par type de document : Manuel de l'utilisateur, Manuel du propriétaire
Alpine CDE-125BT Manuel de l'utilisateur (23 pages)
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Table des matières
Alpine CDE-125BT Manuel de l'utilisateur (5 pages)
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Alpine CDE-125BT Manuel de l'utilisateur (39 pages)
marque: Alpine | Catégorie: Car video systems | Taille: 3.39 MB |
Table des matières
Słowniczek
14
Inne funkcje
16
Odtwarzanie
26
Informacje
29
UNIT ERROR
30
NO DEVICE
30
NO SUPPORT
30
Instalacja
34
Połączenia
36
Alpine CDE-125BT Manuel du propriétaire (36 pages)
marque: Alpine | Catégorie: Car video systems | Taille: 1.41 MB |
Table des matières
Contents
3
F101 T103
11
Terminology
13
About “Text”
16
MP3/WMA/AAC
18
Information
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UNIT ERROR
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NO DEVICE
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NO SUPPORT
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Alpine CDE-125BT Manuel de l'utilisateur (42 pages)
marque: Alpine | Catégorie: Car video systems | Taille: 3.44 MB |
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ОСТОРОЖНО
15
Корневая
16
Меню SETUP
20
USB Memory
27
Информация
32
UNIT ERROR
33
NO DEVICE
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NO SUPPORT
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Соединения
39
Alpine CDE-125BT Manuel du propriétaire (23 pages)
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Alpine CDE-125BT Manuel de l'utilisateur (38 pages)
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Repeat-Modus
12
MP3/WMA/AAC)
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Sprachwahl
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USB-Speicher
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33
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